A Novel Approach for Adder Implementation using Quaternary Signed Digit Number System

Authors:SATISH KUMAR DASARI, M. BHAGYA LAKSHMI DEVI

1089-1096

Design and Simulations of Pulse Improvement Scheme for a Low-Power Pulse-Triggered Flip-Flop

Authors:MOHD ABDUL FAHEEM, J. LINGAIAH

1097-1100

Designing & Analysis of Flip Flops using OBSC and RTPG Integration for Efficient Low Power

Authors:MD.TAJUDDIN, G. BABU

1101-1105

Design of Fuzzy Inference Processor-A MAX-MIN Calculator Circuit for MMF

Authors:H. MADHURI, U. PRADEEP KUMAR

1106-1109

Fixed Hardware Implementation using Built-In Generation of Functional Broadside Tests

Authors:V. NAGARAJU, V. S. PRIYANKA KUMARI, P.RAVEEN

1110-1114

Data Encryption using Pseudo Random Number Generator

Authors:Y. ANKAIAH, P. SIREESHA

1115-1118

High Speed and Area Efficient Radix-22 Feed Forward FFT Architecture

Authors:ARRA ASHOK, S.N.CHANDRASHEKHAR

1119-1123

High Performance Hardware Implementation of AES using Minimal Resources

Authors:DARAM MALAKONDA, KANDULA RAVI KUMAR, ANANDA BABU BATTU

1124-1128

Design and Implementation of 32-Bit Unsigned Multiplier using CLAA and CSLA

Authors:DEGALA PAVAN KUMAR, KANDULA RAVI KUMAR, B.V.MAHALAKSHMI

1129-1133

Optimized Reversible Vedic Multipliers for High Speed Low Power Operations

Authors:GOPATHOTI VINOD KUMAR, KANDULA RAVI KUMAR, ANANDA BABU BATTU

1134-1139